Q1 Instruction Set
Contents
Registers
| Name |
Width |
Description |
| A |
8 bits |
ALU result |
| B |
8 bits |
First ALU source |
| C |
8 bits |
Second ALU source |
| X |
16 bits |
Index register (divided into XL and XH) |
| P |
16 bits |
Program counter |
| N |
16 bits |
Next program counter |
| I |
8 bits |
Instruction latch |
| O |
16 bits |
Operand latch |
| CF |
1 bit |
Carry flag |
| ZF |
1 bit |
Zero flag (1 if zero) |
| NF |
1 bit |
Sign flag (1 if negative) |
Jump Instructions
All jump instructions are 3 bytes. The first nibble is 0000 to indicate
a jump instruction. The second nibble is the type of jump. All jumps are
absolute to the specified address.
| Opcode |
Mnemonic |
Description |
C |
Z |
N |
| 0000 0000 |
J addr |
Jump to addr |
- | - | - |
| 0000 0001 |
JC addr |
Jump if CF to addr |
- | - | - |
| 0000 0010 |
JZ addr |
Jump if ZF to addr |
- | - | - |
| 0000 0011 |
JCZ addr |
Jump if CF and ZF to addr |
- | - | - |
| 0000 0100 |
JN addr |
Jump if NF to addr |
- | - | - |
| 0000 0101 |
JCN addr |
Jump if CF and NF to addr |
- | - | - |
| 0000 0110 |
JZN addr |
Jump if ZF and NF to addr |
- | - | - |
| 0000 0111 |
JCZN addr |
Jump if CF, ZF, and NF to addr |
- | - | - |
| 0000 1000 |
C addr |
X <- P and jump to addr |
- | - | - |
| 0000 1001 |
CC addr |
If CF, X <- P and jump to addr |
- | - | - |
| 0000 1010 |
CZ addr |
If ZF, X <- P and jump to addr |
- | - | - |
| 0000 1011 |
CCZ addr |
If CF and ZF, X <- P and jump to addr |
- | - | - |
| 0000 1100 |
CN addr |
If NF, X <- P and jump to addr |
- | - | - |
| 0000 1101 |
CCN addr |
If CF and NF, X <- P and jump to addr |
- | - | - |
| 0000 1110 |
CZN addr |
If ZF and NF, X <- P and jump to addr |
- | - | - |
| 0000 1111 |
CCZN addr |
If CF, ZF, and NF, X <- P and jump to addr |
- | - | - |
Load/Store Instructions
All load/store instructions are 3 bytes. The first nibble is 0001 to
indicate a load/store instruction. The second nibble is the type of
load/store instruction. All loads and stores are indirect through the
specified absolute address.
| Opcode |
Mnemonic |
Description |
C |
Z |
N |
| 0001 0000 |
LDB addr |
B <- [addr] |
- | - | - |
| 0001 0001 |
LDC addr |
C <- [addr] |
- | - | - |
| 0001 0010 |
LXH addr |
XH <- [addr] |
- | - | - |
| 0001 0011 |
LXL addr |
XL <- [addr] |
- | - | - |
| 0001 0100 |
STB addr |
[addr] <- B |
- | - | - |
| 0001 0101 |
STC addr |
[addr] <- C |
- | - | - |
| 0001 0110 |
SXH addr |
[addr] <- XH |
- | - | - |
| 0001 0111 |
SXL addr |
[addr] <- XL |
- | - | - |
| 0001 1000 |
STA addr |
[addr] <- A |
- | - | - |
Math Instructions
All math instructions are 1 byte. The first nibble is 0010 to indicate
a math instruction. The second nibble specifies the function.
| Opcode |
Mnemonic |
Description |
C |
Z |
N |
| 0010 0000 |
AND |
A <- B AND C |
0 | * | * |
| 0010 0001 |
OR |
A <- B OR C |
0 | * | * |
| 0010 0010 |
SHL |
A <- B << 1 |
* | * | * |
| 0010 0011 |
SHR |
A <- B >> 1 |
* | * | 0 |
| 0010 0100 |
ADD |
A <- B + C |
* | * | * |
| 0010 0101 |
INC |
A <- B + 1 |
* | * | * |
| 0010 0110 |
DEC |
A <- B - 1 |
* | * | * |
| 0010 0111 |
NOT |
A <- NOT B |
0 | * | * |
| 0010 1000 |
CLR |
A <- 0 |
0 | 1 | 0 |
Other Instructions
All instructions of this class are 1 byte. The first nibble is 0011. The
second nibble indicates the function.
| Opcode |
Mnemonic |
Description |
C |
Z |
N |
| 0011 0000 |
MAB |
B <- A |
- | - | - |
| 0011 0001 |
MAC |
C <- A |
- | - | - |
| 0011 0010 |
SAX |
[X] <- A |
- | - | - |
| 0011 0011 |
SBX |
[X] <- B |
- | - | - |
| 0011 0100 |
SCX |
[X] <- C |
- | - | - |
| 0011 0101 |
LBX |
B <- [X] |
- | - | - |
| 0011 0110 |
LCX |
C <- [X] |
- | - | - |
| 0011 0111 |
RET |
P <- X (jump to X) |
- | - | - |
| 0011 1000 |
HLT |
Halt |
- | - | - |